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1 ? cdp1802ac/3 high-reliability cmos 8-bit microprocessor the cdp1802a/3 high - reliability lsi cmos 8 - bit register oriented central - processing unit (cpu) is designed for use as a general purpose computing or control element in a wide range of stored - program systems or products. the cdp1802a/3 includes all of the circuits required for fetching, interpreting, and exec uting instructions which have been stored in standard types of memories. extensive input/output (i/o) control fe atures are also provided to facilitate system design. the 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. the 1800 series cpu also provides a synchronous interface to memories and extern al controllers for i/o devices, and minimizes the cost of interf ace controllers. further, the i/o interface is capable of suppor ting devices operating in polled, interrupt - driven, or direct memory - access modes. the cdp1802ac/3 is functionally identical to its predecessor, the cdp1802. the ?a? version includes some performance enhancements and can be used as a direct replacement in systems using the cdp1802. this type is supplied in a 40 ld dual - in - line sidebrazed ceramic package (d suffix). features for use in aerospace, military, and critical industrial equipment ? minimum instruction fetch - execute time of 4.5s (maximum clock frequency of 3.6mhz) at v dd =5v, t a = +25c ? operation over the full military temperature range . . . . . . . . . . . . . . . -55c to +125c ? any combination of stan dard ram and rom up to 65,536 bytes ? 8-bit parallel organization with bi-direc tional data bus and multiplexed address bus ? 16x16 matrix of registers for use as multiple program counters, data pointers , or data registers ? on-chip dma, interrupt, and flag inputs ? high noise immunity . . . . . . . . . . . . . . . . . . 30% of v dd ? pb-free (rohs compliant) ordering information part number part marking temp. range ( c) clock frequency at 5v package pkg dwg. # CDP1802ACD3 CDP1802ACD3 -55 to +125 up to 3.2mhz 40 ld sbdip d40.6 note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 term ination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. fn1441.3 data sheet october 17, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2002, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn1441.3 october 17, 2008 pinout cdp1802ac/3 (40 ld sbdip) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 clock wait clear q sc1 sc0 mrd bus 7 bus 6 bus 5 bus 4 bus 3 bus 2 bus 1 bus 0 v cc n2 n1 n0 v ss 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd xtal dma in dma out interrupt mwr tpa tpb ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ef1 ef2 ef3 ef4 cdp1852 input port data cs1 cs2 cdp1852 output port clock cs1 cs2 ma0?7 n0 mrd mwr n1 tpb data tpa cdp1802 8?bit cpu mrd ma0?4 mwr cs cdp1824 32 byte ram ma0?7 data ceo tpa mrd 8?bit data bus address bus cdp1833 1k?rom data figure 1. typical cdp1802a/3 small microprocessor system cdp1802ac/3
3 fn1441.3 october 17, 2008 cpu block diagram mux ma7 ma5 ma3 ma1 ma0 ma2 ma4 ma6 memory address lines i/o flags alu b d df incr/ decr a r(0).1 r(0).0 r(1).0 r(1).1 r(2).1 r(2).0 r(9).0 r(a).0 r(a).1 r(9).1 r(e).1 r(f).1 r(f).0 r(e).0 register array 8-bit bidirectional data bus latch and decode r xtp i n n1 n0 n2 i/o commands bus 0 bus 1 bus 2 bus 3 bus 4 bus 5 bus 6 bus 7 to instruction decode control and timing logic clock logic i/o requests control ef1 ef3 ef2 ef4 dma out dma in int clear wait clock xtal sco sci q logic tpa tpb mwr mrd system state codes timing cdp1802ac/3 cdp1802ac/3
4 fn1441.3 october 17, 2008 absolute maximum rati ngs thermal information dc supply voltage range, (v dd ) (all voltages referenced to v ss terminal) cdp1802ac/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) sbdip package . . . . . . . . . . . . . . . . . . 55 15 device dissipation per output transistor t a = full package temperature range . . . . . . . . . . . . . . .100mw operating temperature range (t a ) package type d. . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range (t stg ) . . . . . . . . . . . .-65c to +150c lead temperature (during soldering) at distance 1/16 1/32 in. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. recommended operating conditions t a = full package temperature range. for maxi mum reliability, operating conditions should be selected so that operation is always within the following ranges. parameters with min and/or max limits are 100% tested at +25c, unl ess otherwise specified. temperature limits established by charac terization and are not production tested. parameter min max units dc operating voltage range 4 6.5 v input voltage range v ss v dd v maximum clock input rise or fall time - 1 s performance specifications parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establis hed by characterization and are not production tested. parameter v dd (v) - 55c to +25c +125c units minimum instruction time (note 3) 5 4.5 5.9 s maximum dma transfer rate 5 450 340 kbytes/s maximum clock input frequency, load capacitance (c l ) = 50pf, f cl 5 dc-3.6 dc-2.7 mhz note: 3. equals 2 machine cycles - one fetch an d one execute operation for all instructi ons except long branch and long skip, which re quire 3 machine cycles - one fetch and two execute operations. static electrical specifications all limits are 100% tested. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limit s established by charac terization and are not production tested. parameter conditions -55c, +25c +125c units v out (v) v in, (v) v cc, v dd (v) (note 4) min max min max quiescent device current, i dd - - 5 - 100 - 250 a output low drive (sink) current (except xtal ), i ol 0.4 0, 5 5 1.20 - 0.90 - ma xtal 0.4 5 5 185 - 140 - a output high drive (source) current (except xtal ), i oh 4.6 0, 5 5 - -0.30 - -0.20 ma xtal 4.6 0 5 - -135 - -100 a output voltage low-level, v ol - 0, 5 5 - 0.1 - 0.2 v cdp1802ac/3 cdp1802ac/3
5 fn1441.3 october 17, 2008 output voltage high-level, v oh - 0, 5 5 4.9 - 4.8 - v input low voltage, v il 0.5, 4.5 - 5 - 1.5 - 1.5 v input high voltage, v ih 0.5, 4.5 - 5 3.5 - 3.5 - v input leakage current, i in any input 0, 5 5 - 1 - 5 a three-state output leakage current, i out 0, 5 0, 5 5 - 1 - 5 a note: 4. 5v level characteristics apply to part no. cdp1802ac/3, and 5v and 10v level characteristics apply to part no. cdp1802a/3. timing specifications as a function of t (t = 1/fclock), c l = 50 pf. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by c haracterization and are not production tested. parameter v dd (v) limits ( note 5) units -55c, +25c +125c high-order memory-address byte setup to tpa time, t su 5 2t-450 2t-580 ns high-order memory-address byte hold after tpa time, t h 5 t/2 +0 t/2 +0 ns low-order memory-address byte hold after wr time, t h 5t-30t-40ns cpu data to bus hold after wr time, t h 5 t-170 t-250 ns required memory access time address to data, t acc 5 5t-300 5t-400 ns note: 5. these limits are not directly tested. implicit specifications (note 6) t a = -55c to +25c. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. parameter symbol v dd (v) typical values units typical total power dissipation idle ?00? at m(0000), c l = 50pf f = 2mhz - 5 4 mw effective input capacitance any input - c in -5pf effective three-state terminal capacitance data bus - - - 7.5 pf minimum data retention voltage - v dr -2.4v data retention current - i dr 2.4 10 a note: 6. these specifications are not tested. ty pical values are provided for guidance only. static electrical specifications all limits are 100% tested. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limit s established by charac terization and are not production tested. (continued) parameter conditions -55c, +25c +125c units v out (v) v in, (v) v cc, v dd (v) (note 4) min max min max cdp1802ac/3 cdp1802ac/3
6 fn1441.3 october 17, 2008 dynamic electrical specifications c l = 50pf, timing measurement at 0.5 v dd point. parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits established by characterization and are not production tested. parameters v dd (v) -55c to +25c +125c units min max min max progagation delay times, t plh , t phl clock to tpa, tpb 5 - 275 - 370 ns clock-to-memory high address byte, t plh , t phl 5 - 725 - 950 ns clock-to-memory low address byte valid, t plh , t phl 5 - 340 - 425 ns clock to mrd , t plh , t phl 5 - 340 - 425 ns clock to mwr , t plh , t phl 5 - 275 - 370 ns clock to (cpu data to bus) valid, t plh , t phl 5 - 430 - 550 ns clock to state code, t plh , t phl 5 - 440 - 550 ns clock to q, t plh , t phl 5 - 375 - 475 ns clock to n (0 to 2), t plh , t phl 5 - 400 - 525 ns interface timing requirements (note 7) data bus input setup, t su 510-10-ns data bus input hold, t h 5 175 - 230 - ns dma setup, t su 510-10-ns dma hold, t h 5 200 - 270 - ns interrupt setup, t su 510-10-ns interrupt hold, t h 5 175 - 230 - ns wait setup, t su 530-30-ns ef1-4 setup, t su 520-20-ns ef1-4 hold, t h 5 100 - 135 - ns required pulse width times clear pulse width, t wl 5 150 - 200 - ns clock pulse width, t wl 5 140 - 185 - ns note: 7. minimum input setup and hold times required by part cdp1802ac/3. cdp1802ac/3 cdp1802ac/3
7 fn1441.3 october 17, 2008 timing waveforms fetch (read) execute (write) 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 hi byte low byte hi byte low byte clock address tpa tpb mrd mwr data valid input data valid output data figure 1. basic dc timing waveform, one instruction cycle cdp1802ac/3 cdp1802ac/3
8 fn1441.3 october 17, 2008 notes: 8. this timing diagram is us ed to show signal relationships only and does not represent any specific machine cycle. 9. all measurements are referenced to 50% point of the waveforms. 10. shaded areas indicate ?don?t care? or undefined state. multiple transitions may occur during this period. timing waveforms (continued) clock tpa tpb memory mrd mwr (i/o execution q data from dma interrupt ef 1-4 wait clear request request bus to cpu n0, n1, n2 state data from cpu to bus (memory write cycle) (memory address read cycle) codes cycle) t w 00 10 20 30 40 50 60 70 00 01 11 21 31 41 51 61 71 01 0 1 2 3 4 5 6 7 0 t plh t phl t plh t phl t plh , t phl t su t h address byte high order t phl t plh t su t plh , t phl t plh , t phl t plh t h t plh t h t plh , t phl t plh , t phl t plh , t phl address byte low order t phl t plh t phl t plh t phl t plh t plh data latched in cpu t su t h t su t h t su t h interrupt sampled (s1, s2) flag lines sampled (in s1) any negative transition t su t w t su t h figure 2. timing waveform dma sampled (s1, s2, s3) cdp1802ac/3 cdp1802ac/3
9 fn1441.3 october 17, 2008 machine cycle timing waveforms (propagation delays not shown) figure 3. general timing waveforms figure 4. non-memory cycle timing waveforms figure 5. memory write cycle timing waveforms clock tpa tpb machine ma cycle 01 23 45 6701 2345 6701 2345 670 cycle n cycle (n + 1) cycle (n + 2) low address high add low address high add low address high add memory read cycle non memory cycle memory read cycle instruction mrd mwr (high) memory output fetch (s0) execute (s1) fetch (s0) execute allowable memory access valid output valid output ?don?t care? or internal delays high impedance state memory output allowable memory access valid output valid output memory read cycle memory write cycle memory read cycle instruction fetch (s0) execute (s1) fetch (s0) execute cpu output off valid data off valid mwr mrd to memory ?don?t care? or internal delays high impedance state cdp1802ac/3
10 fn1441.3 october 17, 2008 figure 6. memory read cycle timing waveforms figure 7. long branch or long skip cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) memory read cycle memory read cycle memory read cycle instruction fetch (s0) execute (s1) fetch (s0) execute memory output allowable memory access valid output valid output mrd mwr (high) ?don?t care? or internal delays high impedance state valid output memory output allowable memory access valid output valid output memory read cycle memory read cycle memory read cycle instruction fetch (s0) execute (s1) execute (s1) fetch (s0) mrd mwr (high) ?don?t care? or internal delays high impedance state valid output cdp1802ac/3
11 fn1441.3 october 17, 2008 figure 8. input cycle timing waveforms figure 9. output cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) clock 01 23 456 70123456 7 memory output allowable memory access valid output tpa tpb machine instruction mrd n0 - n2 data mwr cycle bus memory read cycle memory write cycle valid data from input device n = 9 - f execute (s1) cycle (n + 1) cycle n fetch (s0) note: user generated signal ?don?t care? or internal delays high impedance state (note) 0 clock 01 23 456 70123456 7 tpa tpb machine instruction cycle execute (s1) cycle (n + 1) cycle n fetch (s0) data bus allowable memory access valid output valid data from memory allowable memory access memory read cycle memory read cycle mrd n0 - n2 data strobe (mrd 2 tpb 2 n) note: user generated signal ?don?t care? or internal delays high impedance state (note) 0 n = 1 - 9 cdp1802ac/3
12 fn1441.3 october 17, 2008 figure 10. dma in cycle timing waveforms figure 11. dma out cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) clock 0123 456701234567 01 23 tpa tpb machine instruction dma-in mrd mwr memory data bus cycle output 45 67 note: user generated signal memory read cycle memory read, write memory write cycle or non-memory cycle ?don?t care? or internal delays high impedance state (note) valid data from input device cycle n fetch (s0) cycle (n+1) execute (s1) cycle (n+2) dma (s2) valid output 01234567012345670123456 clock tpa tpb machine cycle instruction dma out mrd mwr memory output data strobe (s2 2 tpb) cycle n cycle (n + 1) cycle (n + 2) dma (s2) execute (s1) fetch (s0) valid output valid data from memory note: user generated signal memory read cycle memory read, write memory read cycle or non-memory cycle ?don?t care? or internal delays high impedance state (note) (note) cdp1802ac/3
13 fn1441.3 october 17, 2008 figure 12. interrupt cycle timing waveforms performance curves figure 13. typical maximum clock frequency as a function of temperature figure 14. typical maximum clock frequency as a function of supply voltage machine cycle timing waveforms (propagation delays not shown) (continued) 01234567012345670123456 clock tpa tpb machine cycle instruction cycle n cycle (n + 1) cycle (n + 2) interrupt (s3) execute (s1) fetch (s0) mrd mwr interrupt memory output valid output note: user generated signal memory read cycle memory read, write non-memory cycle or non-memory cycle ?don?t care? or internal delays high impedance state (note) (internal) ie 5 4 3 2 1 0 6 7 8 35 45 55 65 75 85 95 105 115 25 125 system maximum clock frequency (f cl ) (mhz) v dd = 5v load capacitance (c l ) = 50pf ambient temperature (t a ) ( c) 345678910 12 2 supply voltage (v dd ) (v) 11 5 4 3 2 1 0 6 7 system maximum clock frequency (f cl ) (mhz) 8 load capacitance (c l ) = 50pf t a = +25c t a = +125c e x t r a p o l a t e d cdp1802ac/3
14 fn1441.3 october 17, 2008 figure 15. typical transition time vs load capacitance figure 16. minimum output high (source) current characteristics figure 17. minimum output low (sink) current characteristics figure 18. typical power dissipation as a function of clock frequency for branch instruction and idle instruction figure 19. typical change in propagation delay as a function of a change in load capacitance performance curves (continued) 50 75 100 125 150 175 200 25 300 250 200 150 100 350 400 0 50 transition time (t thl , t tlh ) (ns) ambient temperature (t a ) = +25c 0 load capacitance (c l ) (pf) t tlh t thl -9 -8 -7 -6 -5 -4 -3 -10 2 3 4 5 6 1 0 -2 -1 output high (source) current (i oh -ma) drain to source voltage (v ds ) (v) gate to source voltage (v gs ) = -5v ambient temperature = -40c to +85c 0 25 20 15 10 5 30 35 123456 7 08910 gate to source voltage (v gs ) = 5v ambient temperature = -40c to +85c output low (sink) current (i ol ) (ma) 0 drain-to-source voltage (v ds ) (v) 10 1 0.1 100 1000 0.01 0.1 1m 10m ambient temperature (t a ) = +25 c clock input frequency (f cl ) (hz) typical power dissipation (p d ) (mw) v c c = v d d = + 5 v v c c = v d d = 5 v ? b r a n c h ? ? i d l e ? idle = ?00? at m (0000) branch = ?3707? at m (8107) 100 75 50 25 0 125 150 50 100 150 200 0 load capacitance ( c l ) (pf) ambient temperature (t a ) = +25c v c c = v d d = 5 v t ph l t p l h v c c = v d d = 5 v propagation delay time ( tplh, tphl) (ns) any output except xtal cdp1802ac/3
15 fn1441.3 october 17, 2008 signal descriptions bus 0 to bus 7 (data bus) 8-bit bidirectional data bus lines. these lines are used for transferring data between the memory, the microprocessor, and i/o devices. n0 to n2 (i/o control lines) activated by an i/o instruction to signal the i/o control logic of a data transfer between memory and i/o interface. these lines can be used to issu e command codes or device selection codes to the i/o devices (independently or combined with the memory byte on the data bus when an i/o instruction is being executed). the n bits are low at all times except when an i/o instruction is being executed. during this time their state is the same as the corresponding bits in the n register. the direction of data flow is defined in the i/o instruction by bit n3 (internally) and is indicated by the level of the mrd signal. mrd = v cc : data from i/o to cpu and memory mrd = v ss : data from memory to i/o ef1 to ef4 (4 flags) these inputs enable the i/o controllers to transfer status information to the pr ocessor. the levels can be tested by the conditional branch instructions. they can be used in conjunction with the interrupt request line to establish interrupt priorities. these flags can also be used by i/o devices to ?call the attention? of the processor, in which case the program must routinely test the status of these flag(s). the flag(s) are sampled at the beginning of every s1 cycle. interrupt , dma-ln , dma-out (3 i/o requests) these inputs are sampled by the cpu during the interval between the leading edge of tpb and the leading edge of tpa. interrupt action - x and p are stored in t after executing current instruction; designator x is set to 2; designator p is set to 1; interrupt enable is reset to 0 (inhibit); and instruction execution is resumed. the interrupt action requires one machine cycle (s3). dma action - finish executing current instruction; r(0) points to memory area for data transfer; data is loaded into or read out of memory; and increment r(0). note: in the event of concurrent dma and interrupt requests, dma-ln has priority followed by dma-out and then interrupt. sc0, sc1 (2 state code lines) these outputs indicate that the cpu is: 1. fetching an instruction 2. executing an instruction 3. processing a dma request, 4. acknowledging an interrupt request. the levels of state code are tabulated in table 1. all states are valid at tpa. h=v cc , l = v ss . tpa, tpb (2 timing pulses) positive pulses that occur on ce in each machine cycle (tpb follows tpa). they are used by i/o controllers to interpret codes and to time interaction with the data bus. the trailing edge of tpa is used by the memory system to latch the higher-order byte of the 16-bit memory address. tpa is suppressed in idle when the cpu is in the load mode. ma0 to ma7 (8 memory address lines) in each cycle, the higher-order byte of a 16-bit cpu memory address appears on the memory address lines ma0-7 first. those bits required by the memory system can be strobed into external address latches by timing pulse tpa. the low order byte of the 16-bit addres s appears on the address lines after the termination of tpa. latching of all 8 higher-order address bits would permit a memory system of 64k bytes. mwr (write pulse) a negative pulse appearing in a memory-write cycle, after the address lines have stabilized. mrd (read level) a low level on mrd in dicates a memory read cycle. it can be used to control three-stat e outputs from the addressed memory which may have a common data input and output bus. if a memory does not have a three-state high-impedance output, mrd is useful for driving memory/bus separator gates. it is also used to indicate the direction of data transfer during an i/o instruction. for additional information see table 4. q single bit output from the cpu which can be set or reset under program control. during seq or req instruction execution, q is set or reset between the trailing edge of tpa and the leading edge of tpb. clock input for externally generated single-phase clock. the clock is counted down internally to 8-clock pulses per machine cycle. table 1. levels of state code state type state code lines sc1 sc0 s0 (fetch) l l s1 (execute) l h s2 (dma) h l s3 (interrupt) h h cdp1802ac/3
16 fn1441.3 october 17, 2008 xtal connection to be used with clock input terminal, for an external crystal, if the on-chip oscillator is utilized. the crystal is connected between terminals 1 and 39 (clock and xtal ) in parallel with a resistance (10m typ). frequency trimming capacitors may be required at terminals 1 and 39. for additional information, see application note an6565. wait , clear (2 control lines) provide four control modes as listed in table 2: v dd , v ss , v cc (power levels) the internal voltage supply v dd is isolated from the input/output voltage supply v cc so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage. v cc must be less than or equal to v dd . all outputs swing from v ss to v cc . the recommended input voltage swing is v ss to v cc . architecture the ?cpu block diagram? is shown on page 3. the principal feature of this system is a r egister array (r) consisting of sixteen 16-bit scratchpad register s. individual registers in the array (r) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled n, p and x. the contents of any register can be directed to any one of the following three paths: 1. the external memory (multiplexed, higher-order byte first, on to 8 memory address lines). 2. the d register (either of the two bytes can be gated to d). 3. the increment/decrement circui t where it is increased or decreased by one and stored back in the selected 16-bit register. the three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. with two exceptions, cpu instruction consists of two 8-clock-pulse machine cycles. th e first cycle is the fetch cycle, and the second and third if necessary, are execute cycles. during the fetch cycle the four bits in the p designator select one of the 16 registers r(p) as the current program counter. the selected register r(p) contains the address of the memory location fr om which the instruction is to be fetched. when the instru ction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the n register. the content of the pr ogram counter is automatically incremented by one so that r(p) is now ?pointing? to the next byte in the memory. the x designator selects one of the 16 registers r(x) to ?point? to the memory for an operand (or data) in certain alu or i/o operations. the n designator can perform the following five functions depending on the type of instruction fetched: 1. designate one of the 16 registers in r to be acted upon during register operations. 2. indicate to the i/o devices a command code or device selection code for peripherals. 3. indicate the specific operat ion to be executed during the alu instructions, types of test to be performed during the branch instruction, or the spec ific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7b). 4. indicate the value to be loaded into p to designate a new register to be used as the program counter r(p). 5. indicate the value to be loaded into x to designate a new register to be used as data pointer r(x). the registers in r can be assi gned by a programmer in three different ways: as program coun ters, as data pointers, or as scratchpad locations (data regist ers) to hold two bytes of data. program counters any register can be the main program counter; the address of the selected register is hel d in the p designator. other registers in r can be used as subroutine program counters. by single instruction the contents of the p register can be changed to effect a ?call? to a subroutine. when interrupts are being serviced, register r(1) is used as the program counter for the user's interrupt servicing routine. after reset, and during a dma operation, r(0) is used as the program counter. at all other times the register designated as program counter is at the discretion of the user. data pointers the registers in r may be used as data pointers to indicate a location in memory. the register designated by x (i.e., r(x)) points to memory for the following instructions (see table 4). 1. alu operations f1 - f5, f7, 74, 75, 77 2. output instructions 61 through 67 3. input instructions 69 through 6f 4. certain miscellaneous instructions - 70 - 73, 78, 60, f0 the register designated by n (i.e., r(n)) points to memory for the ?load d from memory? instructions 0n and 4n and the ?store d? instruction 5n. the r egister designated by p (i.e., the program counter) is used as the data pointer for alu instructions f8 - fd, ff, 7c, 7d , 7f. during these instruction executions, the operation is referred to as ?data immediate?. another important use of r as a data pointer supports the built-in direct-memory-access (dma) function. when a table 2. truth table clear wait mode llload l h reset hlpause hh run cdp1802ac/3
17 fn1441.3 october 17, 2008 dma-in or dma-out request is received, one machine cycle is ?stolen?. this operation occurs at the end of the execute machine cycle in the current in struction. register r(0) is always used as the data pointer during the dma operation. the data is read from (dma-out ) or written into (dma-in) the memory location pointed to by the r(0) register. at the end of the transfer, r(0) is incremented by one so that the processor is ready to act upon the next dma byte transfer request. this featur e in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during crt-display-refresh cycles. data registers when registers in r are used to store bytes of data, four instructions are provided which allow d to receive from or write into either the higher-order or lower-order byte portions of the register designated by n. by this mechanism (together with loading by data immediate) program pointer and data pointer designations are initia lized. also, this technique allows scratchpad registers in r to be used to hold general data. by employing increment or decrement instructions, such registers may be used as loop counters. the q flip-flop an internal flip-flop, q, can be set or reset by instruction and can be sensed by conditional branch instructions. the output of q is also available as a microprocessor output. interrupt servicing register r(1) is always used as the program counter whenever interrupt servicing is initiated. when an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the current instruction), the contents of the x and p registers are stored in the temporary register t, and x and p are set to new values; hex digit 2 in x and hex digit 1 in p. interrupt enable is automatically deac tivated to inhibit further interrupts. the user's interrupt routine is now in control; the contents of t may be saved by m eans of a single instruction (78) in the memory location pointed to by r(x). at the conclusion of the interrupt, the user's routine may restore the pre-interrupted value of x and p with a single instruction (70 or 71). the interrupt enable flip-flop can be activated to permit further interrupts or can be disabled to prevent them. cpu register summary cdp1802 control modes the wait and clear lines provide four control modes as listed in table 3: the functions of the modes are defined as follows: load holds the cpu in the idle execution state and allows an i/o device to load the memory without the need for a ?bootstrap? loader. it modifies the idle condition so that dma-ln operation does not force execut ion of the next instruction. reset registers l, n, q are reset, le is set and 0?s (vss) are placed on the data bus. tpa and tpb are suppressed while reset is held and the cpu is placed in s1. the first machine cycle after termination of reset is an initialization cycle which requires 9 clock pulses. during this cycle the cpu remains in s1 and register x, p, and r(0) are re set. interrupt and dma servicing are suppressed during the initializat ion cycle. the next cycle is an s0, s1, or an s2 but never an s3. with the use of a 71 instruction followed by 00 at memory locations 0000 and 0001, this feature may be used to reset ie, so as to preclude interrupts until ready for them. power-up reset can be realized d 8 bits data register (accumulator) df 1-bit data flag (alu carry) b 8 bits auxiliary holding register r 16 bits 1 of 16 scratchpad registers p 4 bits designates which register is program counter x 4 bits designates which register is data pointer n 4 bits holds low-order instruction digit i 4 bits holds high-order instruction digit t 8 bits holds old x, p after interrupt (x is high nibble) le 1-bit interrupt enable q 1-bit output flip-flop table 3. control modes clear wait mode llload l h reset hlpause h h run cdp1802ac/3
18 fn1441.3 october 17, 2008 by connecting an rc network directly to the clear pin, since it has a schmitt triggered input; see figure 20. pause stops the internal cpu timing generator on the first negative high-to-low transition of the input clock. the oscillator continues to operate, but su bsequent clock transitions are ignored. run may be initiated from the paus e or reset mode functions. if initiated from pause, the cpu resumes operation on the first negative high-to-low transition of the input clock. when initiated from the reset operation, the first machine cycle following reset is always t he initializati on cycle. the initialization cycle is then followed by a dma (s2) cycle or fetch (s0) from location 0000 in memory. run-mode state transitions the cpu state transitions when in the run and reset modes are shown in figure 21 . each machine cycle requires the same period of time, 8-clock pulses, except the initialization cycle, which requires 9-clock pulses. the execution of an instruction r equires either two or three machine cycles, s0 followed by a single s1 cycle or two s1 cycles. s2 is the response to a dma request and s3 is the interrupt response. table 5 shows the conditions on data bus and memory address lines during all machine states. instruction set the cpu instruction summary is given in table 4. hexadecimal notation is used to refer to the 4-bit binary codes. in all registers bits are numbere d from the least significant bit (lsb) to the most significant bit (msb) starting with 0. r(w): register designated by w, where: w = n or x, or p r(w).0: lower order byte of r(w) r(w).1: higher order byte of r(w) operation notation m(r(n)) d; r(n) + 1 r(n) this notation means: the memory byte pointed to by r(n) is loaded into d, and r(n) is incremented by 1. . clear v cc r s c cdp1802 3 the rc time constant should be greater than the oscillator start-up time (typically 20ms) figure 20. reset diagram figure 21. state transition diagram s2 dma s1 reset s1 execute s0 fetch s3 int s1 init dma dma dma ? int dma dma idle ? dma ? int force s1 (long branch, dma ? idle ? int dma dma int ? dma long skip, nop, etc.) priority: force s0, s1 dma in dma out int int ? dma cdp1802ac/3
19 fn1441.3 october 17, 2008 table 4. instruction summary (see notes 11 through 16) instruction mnemonic op code operation memory reference load via n ldn 0n m(r(n)) d; for n not 0 load advance lda 4n m(r(n)) d; r(n) + 1 r(n) load via x ldx f0 m(r(x)) d load via x and advance ldxa 72 m(r(x)) d; r(x) + 1 r(x) load immediate ldl f8 m(r(p)) d; r(p) + 1 r(p) store via n str 5n d m(r(n)) store via x and decrement stxd 73 d m(r(x)); r(x) - 1 r(x) register operations increment reg n inc 1n r(n) + 1 r(n) decrement reg n dec 2n r(n) - 1 r(n) increment reg x irx 60 r(x) + 1 r(x) get low reg n glo 8n r(n).0 d put low reg n plo an d r(n).0 get high reg n ghl 9n r(n).1 d put high reg n phi bn d r(n).1 logic operations (note 11) or or f1 m(r(x)) or d d or immediate orl f9 m(r(p)) or d d; r(p) + 1 r(p) exclusive or xor f3 m(r(x)) xor d d exclusive or immediate xri fb m(r(p)) xor d d; r(p) + 1 r(p) and and f2 m(r(x)) and d d and immediate anl fa m(r(p)) and d d; r(p) + 1 r(p) shift right shr f6 shift d right, lsb(d) df, 0 msb(d) shift right with carry shrc 76 (note 12) shift d right, lsb(d) df, df msb(d) ring shift right rshr 76 (note 12) shift d right, lsb(d) df, df msb(d) shift left shl fe shift d left, msb(d) df, 0 lsb(d) shift left with carry shlc 7e (note 12) shift d left, msb(d) df, df lsb(d) ring shift left rshl 7e (note 12) shift d left, msb(d) df, df lsb(d) arithmetic operations (note 11) add add f4 m(r(x)) + d df, d add immediate adl fc m(r(p)) + d df, d; r(p) + 1 r(p) add with carry adc 74 m(r(x)) + d + df df, d add with carry, immediate adcl 7c m(r(p)) + d + df df, d; r(p) + 1 r(p) subtract d sd f5 m(r(x)) - d df, d subtract d immediate sdl fd m(r(p)) - d df, d; r(p) + 1 r(p) subtract d with borrow sdb 75 m(r(x)) - d - (not df) df, d cdp1802ac/3
20 fn1441.3 october 17, 2008 subtract d with borrow, immediate sdbl 7d m(r(p)) - d - (not df) df, d; r(p) + 1 r(p) subtract memory sm f7 d-m(r(x)) df, d subtract memory immediate sml ff d-m(r(p)) df, d; r(p) + 1 r(p) subtract memory with borrow smb 77 d-m(r(x))-(not df) df, d subtract memory with borrow, i mmediate smbl 7f d-m(r(p))-(not df) df, d; r(p) + 1 r(p) branch instructions - short branch short branch br 30 m(r(p)) r(p).0 no short branch (see skp) nbr 38 (note 12) r(p) + 1 r(p) short branch if d = 0 bz 32 if d = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if d not 0 bnz 3a if d not 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if df = 1 bdf 33 (note 12) if df = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if pos or zero bpz short branch if equal or greater bge short branch if df = 0 bnf 3b (note 12) if df = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if minus bm short branch if less bl short branch if q = 1 b q31if q = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if q = 0 bnq 39 if q = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef1 = 1 (ef1 = v ss )b134if ef1 =1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef1 = 0 (ef1 = v cc ) bn1 3c if ef1 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef2 = 1 (ef2 = v ss ) b2 35 if ef2 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef2 = 0 (ef2 = v cc ) bn2 3d if ef2 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef3 = 1 (ef3 = v ss ) b3 36 if ef3 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef3 = 0 (ef3 = v cc ) bn3 3e if ef3 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef4 = 1 (ef4 = v ss ) b4 37 if ef4 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef4 = 0 (ef4 = v cc ) bn4 3f if ef4 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) branch instructions - long branch long branch lbr c0 m(r(p)) r(p). 1, m(r(p) + 1) r(p).0 no long branch (see lskp) nlbr c8 (note 12) r(p) = 2 r(p) long branch if d = 0 lbz c2 lf d = 0, m(r(p)) r(p).1, m(r(p) +1) r(p).0, else r(p) + 2 r(p) long branch if d not 0 lbnz ca if d not 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if df = 1 lbdf c3 lf df = 1, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if df = 0 lbnf cb if df = 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if q = 1 lbq c1 if q = 1, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) table 4. instruction summary (see notes 11 through 16) (continued) instruction mnemonic op code operation cdp1802ac/3
21 fn1441.3 october 17, 2008 long branch lf q = 0 lbnq c9 lf q = 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0 eise r(p) + 2 r(p) skip instructions short skip (see nbr) skp 38 (note 12) r(p) + 1 r(p) long skip (see nlbr) lskp c8 (note 12) r(p) + 2 r(p) long skip if d = 0 lsz ce if d = 0, r(p) + 2 r(p), else continue long skip if d not 0 lsnz c6 if d not 0, r(p) + 2 r(p), else continue long skip if df = 1 lsdf cf if df = 1, r(p) + 2 r(p), else continue long skip if df = 0 lsnf c7 if df = 0, r(p) + 2 r(p), else continue long skip lf q = 1 lsq cd if q = 1, r(p) + 2 r(p), else continue long skip if q = 0 lsnq c5 if q = 0, r(p) + 2 r(p), else continue long skip if le = 1 lsle cc if ie = 1, r(p) + 2 r(p), else continue control instructions idle ldl 00 (note 13) wait for dma or interrupt; m(r(0)) bus no operation nop c4 continue set p sep dn n p set x sex en n x set q seq 7b 1 q reset q req 7a 0 q save sav 78 t m(r(x)) push x, p to stack mark 79 (x, p) t; ( x , p ) m(r(2)), then p x; r(2) - 1 r(2) return ret 70 m(r(x)) (x, p); r(x) + 1 r(x), 1 le disable dls 71 m(r(x)) (x, p); r(x) + 1 r(x), 0 le input - output byte transfer output 1 out 1 61 m(r(x)) bus; r(x) + 1 r(x); n lines = 1 output 2 out 2 62 m(r(x)) bus; r(x) + 1 r(x); n lines = 2 output 3 out 3 63 m(r(x)) bus; r(x) + 1 r(x); n lines = 3 output 4 out 4 64 m(r(x)) bus; r(x) + 1 r(x); n lines = 4 output 5 out 5 65 m(r(x)) bus; r(x) + 1 r(x); n lines = 5 output 6 out 6 66 m(r(x)) bus; r(x) + 1 r(x); n lines = 6 output 7 out 7 67 m(r(x)) bus; r(x) + 1 r(x); n lines = 7 input 1 inp 1 69 bus m(r(x)); bus d; n lines = 1 input 2 inp 2 6a bus m(r(x)); bus d; n lines = 2 input 3 inp 3 6b bus m(r(x)); bus d; n lines = 3 input 4 inp 4 6c bus m(r(x)); bus d; n lines = 4 input 5 inp 5 6d bus m(r(x)); bus d; n lines = 5 table 4. instruction summary (see notes 11 through 16) (continued) instruction mnemonic op code operation cdp1802ac/3
22 fn1441.3 october 17, 2008 input 6 inp 6 6e bus m(r(x)); bus d; n lines = 6 input 7 inp 7 6f bus m(r(x)); bus d; n lines = 7 notes: (for table 4) 11. the arithmetic operations and the shift instructions are the only instructions that can alter the df. after an add instruction: df = 1 denotes a carry has occurred df = 0 denotes a carry has not occurred after a subtract instruction: df = 1 denotes no borrow. d is a true positive number df = 0 denotes a borrow. d is two?s complement the syntax ?-(not df)? denotes the subtraction of the borrow. 12. this instruction is associated with more than one mnemonic. each mnemoni c is individually listed. 13. an idle instruction initiates a repeati ng s1 cycle. the processor will conti nue to idle until an i/o request (interrupt , dma-ln , or dma- out ) is activated. when the request is ack nowledged, the idle cycle is terminated and t he i/o request is serviced, and then normal o peration is resumed. 14. long-branch, long-skip and no op instructions require three cycles to complete (1 fetch + 2 execute). long-branch instructions are three bytes long. the first byte specifies the condition to be tested; and the second and third by te, the branching address. the long-branch instructions can: a. branch unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. effect an unconditional no branch if the tested condition is met, then branching takes place; t he branching address bytes are loaded in the high-and-low order by tes of the cur- rent program counter, respectively. this operat ion effects a branch to any memory location. if the tested condition is not met, the branching address bytes are skipped over, and the next in struction in sequence is fetch ed and executed. this operation is taken for the case of unconditional no branch (nlbr). 15. the short-branch instructions are two by tes long. the first byte specifies the c ondition to be tested, and the second specif ies the branching address. the short branch instruction can: a. branch unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. test the status (1 or 0) of the four ef flags f. effect an unconditional no branch if the tested condition is met, then branching takes place; the branching address byte is loaded in to the low-order byte positi on of the current program counter. this effects a branch within the current 256-b yte page of the memory, i.e., the page which holds the branching address. if the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched and ex ecuted. this same action is taken in the case of unconditional no branch (nbr). 16. the skip instructions are one byte long. there is one un conditional short-skip (skp) and eight long-skip instructions. the unconditional short-skip instruction takes 2 cycles to complete (1 fetch + 1 execut e). its action is to skip over the byte following it. then the next instruction in sequence is fetc hed and executed. this skp instruction is identical to the unconditional no-branch inst ruction (nbr) except that the skipped-over byte is not considered part of the program. the long-skip instructions take three cycl es to complete (1 fetch + 2 execute). they can: a. skip unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. test for ie = 1 if the tested condition is met, then long skip takes place; the curr ent program counter is incremented twice. thus two bytes ar e skipped over, and the next instruction in sequence is fetched and executed. if the tested condition is not met, then no action is taken. exec ution is continued by fetching the next instruction in sequence. table 4. instruction summary (see notes 11 through 16) (continued) instruction mnemonic op code operation cdp1802ac/3
23 fn1441.3 october 17, 2008 table 5. conditions on data bus and memory address lines during all machine states state i n symbol operation data bus memory address mrd mwr n lines notes s1 reset 0 i, n, q, x, p; 1 le 00 xxxx 1 1 0 17 initialize, not programmer accessible 0000 r 00 xxxx 1 1 0 18 s0 fetch mrp l, n; rp + 1 rp mrp rp 0 1 0 19 s1 0 0 ldl idle mr0 ro 0 1 0 20, fig. 6 01 - f ldn mrn d mrn rn 0 1 0 fig. 6 10 - f inc rn + 1 rn float rn 1 1 0 fig. 4 20 - f dec rn - 1 rn float rn 1 1 0 fig. 4 30 - f short branch taken: mrp rp.0 not taken; rp + 1 rp mrp rp 0 1 0 fig. 6 40 - f lda mrn d; rn + 1 rn mrn rn 0 1 0 fig. 6 50 - f str d mrn d rn 1 0 0 fig. 5 60 irx rx + 1 rx mrx rx 0 1 0 fig. 5 61 out 1 mrx bus; rx + 1 rx mrx rx 0 1 1 fig. 9 2 out 2 2fig. 9 3 out 3 3fig. 9 4 out 4 4fig. 9 5 out 5 5fig. 9 6 out 6 6fig. 9 7 out 7 7fig. 9 9 inp 1 bus mrx, d data from i/o device rx 1 0 1 fig. 8 a inp 2 2fig. 8 b inp 3 3fig. 8 c inp 4 4fig. 8 d inp5 5fig. 8 e inp6 6fig. 8 f inp7 7fig. 8 70 ret mrx (x, p); rx + 1 rx; 1 le mrx rx 0 1 0 fig. 6 1 dls mrx (x, p); rx + 1 rx; 0 le mrx rx 0 1 0 fig. 6 2 ldxa mrx d; rx + 1 rx mrx rx 0 1 0 fig. 6 3 stxd d mrx; rx - 1 rx d rx 1 0 0 fig. 5 4 adc mrx + d + df df, d mrx rx 0 1 0 fig. 6 5 sdb mrx - d - dfn df, d mrx rx 0 1 0 fig. 6 6 shrc lsb(d) df; df msb(d) float rx 1 1 0 fig. 4 7 smb d - mrx - dfn df, d mrx rx 0 1 0 fig. 6 8 sav t mrx t rx 1 0 0 fig. 5 cdp1802ac/3
24 fn1441.3 october 17, 2008 s1 7 9 mark (x, p) t, mr2; p x; r2 - 1 r2 tr2100fig. 5 a req 0 q float rp 1 1 0 fig. 4 b seq 1 q float rp 1 1 0 fig. 4 c adcl mrp + d + df df, d; rp + 1 mrp rp 0 1 0 fig. 6 d sdbl mrp - d - dfn df, d; rp + 1 mrp rp 0 1 0 fig. 6 e shlc msb(d) df; df lsb(d) float rp 1 1 0 fig. 4 f smbl d - mrp - dfn df, d; rp + 1 mrp rp 0 1 0 fig. 6 80 - f glo rn.0 drn.0rn110fig. 4 90 - f ghl rn.1 drn.1rn110fig. 4 a0 - f plo d rn.0 d rn 1 1 0 fig. 4 b0 - f phi d rn.1 d rn 1 1 0 fig. 4 s1#1 c 0 - 3, 8 - b long branch taken: mrp b; rp + 1 rp mrp rp 0 1 0 fig. 7 #2 taken: b rp.1; mrp rp.0 m(rp + 1) rp + 1 0 1 0 fig. 7 s1#1 not taken: rp + 1 rp mrp rp 0 1 0 fig. 7 #2 not taken: rp + 1 rp m(rp + 1) rp + 1 0 1 0 fig. 7 s1#1 5 6 7 c d e f long skip taken: rp + 1 rp mrp rp 0 1 0 fig. 7 #2 taken: rp + 1 rp m(rp + 1) rp + 1 0 1 0 fig. 7 s1#1 not taken: no operation mrp rp 0 1 0 fig. 7 #2 not taken: no operation mrp rp 0 1 0 fig. 7 s1#1 4 nop no operation mrp rp 0 1 0 fig. 7 #2 no operation mrp rp 0 1 0 fig. 7 s1 d 0 - f sep n pnnrn110fig. 4 e0 - f sex n xnnrn110fig. 4 s1 f 0 ldx mrx d mrx rx 0 1 0 fig. 6 1 2 3 4 5 7 or and xor add sd sm mrx or d d mrx and d d mrx xor d d mrx + d df, d mrx - d df, d d - mrx df, d mrx rx 0 1 0 fig. 6 6 shr lsb(d) df; 0 msb(d) float rx 1 1 0 fig. 4 table 5. conditions on data bus and memory addr ess lines during all machine states (continued) state i n symbol operation data bus memory address mrd mwr n lines notes cdp1802ac/3
25 fn1441.3 october 17, 2008 operating and handling considerations handling all inputs and outputs of intersil cmos devices have a network for electrostatic protection during handling. operating operating voltage during operation near the maximum supply voltage limit care should be taken to avoid or s uppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause v dd - v ss to exceed the absolute maximum rating. input signals to prevent damage to the input protection circuit, input signals should never be greater than v dd nor less than v ss . input currents must not exc eed 10ma even when the power supply is off. unused inputs a connection must be provided at every input terminal. all unused input terminals must be connected to either v dd or v ss , whichever is appropriate. output short circuits shorting of outputs to v dd or v ss may damage cmos devices by exceeding the maximum device dissipation. s1 f 8 ldl mrp d; rp + 1 rp mrp rp 0 1 0 fig. 6 9 orl mrp or d d; rp + 1 rp a anl mrp and d d; rp + 1 rp b xrl mrp xor d d; rp + 1 rp c adl mrp + d df, d; rp + 1 rp d sdl mrp - d df, d; rp + 1 rp f sml d - mrp df, d; rp +1 rp e shl msb(d) df; 0 lsb(d) float rp 1 1 0 fig. 4 s2 dma in bus mr0; r0 + 1 r0 data from i/o device r0 1 0 0 22, fig. 10 dmaout mr0 bus; r0 + 1 r0 mr0 r0 0 1 0 22, fig. 11 s3 interrupt x, p t; 0 le, 1 p; 2 x float rn 1 1 0 fig. 12 s1 load idle (clear , walt = 0) m(r0 - 1) r0 - 1 0 1 0 21, fig. 6 notes: 17. le = 1, tpa, tpb suppressed, state = s1. 18. bus = 0 for entire cycle. 19. next state always s1. 20. wait for dma or interrupt. 21. suppress tpa, wait for dma. 22. in request has priority over out request. 23. see ?timing waveforms? beginning on page 7 and figures 3 thro ugh 12 for ?machine cyle timing waveforms beginning on page 9. table 5. conditions on data bus and memory addr ess lines during all machine states (continued) state i n symbol operation data bus memory address mrd mwr n lines notes cdp1802ac/3
26 fn1441.3 october 17, 2008 burn-in circuit type v dd temperature time cdp1802ac 7v +125c 160 hours figure 22. bias/static burn-in circuit v dd v dd nc nc v dd v dd nc 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 all resistors are 47k 20% cdp1802ac/3
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn1441.3 october 17, 2008 cdp1802ac/3 ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d40.6 mil-std-1835 cdip2-t40 (d-5, configuration c) 40 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 2.096 - 53.24 4 e 0.510 0.620 12.95 15.75 4 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n40 408 rev. 0 4/94

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